In many situations, integrated circuit chips include circuitry for comparing like ordered bits of two multi-bit bytes or words. FIG. 1 is a circuit diagram of a prior art complementary metal oxide semiconductor (CMOS) circuit for deriving a bi-level output having (1) a first value in response to any like ordered bits of first and second 8-bit bytes having different values and (2) a second value in response to all of the like ordered bits of the 8-bit bytes having the same value. In other words, the circuit of FIG. 1 derives a binary output having (1) the first value in response to any of A.sub.i {character pullout} B.sub.i (where A.sub.i is the binary bit of order i of the first word, B.sub.i is the binary bit of order i of the second word and i is each of 0, 1 . . . 7) and (2) the second value in response to each of A.sub.i =B.sub.i.
The circuit of FIG. 1 includes a separate comparator 10, 11, 12 . . . 16, 17 for each of the eight like ordered bits A.sub.i +B.sub.i of the two bytes. Because all of comparators 10-17 are the same, the description of comparator 10 which is responsive to bits A.sub.0 and B.sub.0 of the first and second bytes suffices for the remaining comparators.
Comparator 10 includes signal input terminals 20 and 22 responsive to sources 24 and 26 which derive the binary bits A.sub.0 and B.sub.0, respectively. Comparator 10 also includes signal output terminal 28 and grounded terminal 30. Comparator 10 includes internal circuitry such that the ground voltage at terminal 30 is coupled to output terminal 28 in response to the binary values of bits A.sub.0 and B.sub.0 differing from each other and for decoupling terminal 28 from grounded terminal 30 in response to bits A.sub.0 and B.sub.0 having the same binary values. In other words, terminal 28 is grounded in response to A.sub.0 =1 while B.sub.0 =0 or in response to A.sub.0 =0 while B.sub.0 =1. Terminal 28 is decoupled from ground terminal 30 in response to A.sub.0 =B.sub.0 =1 or while A.sub.0 =B.sub.0 =0.
To achieve the aforementioned results, comparator 10 includes four N-channel field effect transistors (FETs) 41-44. FETs 41 and 42 have source drain paths connected in a first-series circuit with each other between output terminal 28 and ground terminal 30. FETs 43 and 44 have source drain paths connected in a second series circuit with each other between terminals 28 and 30. FETs 41 and 43 have gate electrodes respectively connected directly to the A.sub.0 output of source 24 and connected to the output of source 24 via inverter 46. FETs 42 and 44 have gate electrodes connected to the B.sub.0 signal derived by source 26 such that the gate of FET 42 is connected to source 26 via inverter 48 while the gate of FET 44 is connected directly to the B.sub.0 output of source 26. Typically, each of inverters 46 and 48 includes a pair of complementary FETs having series connected source drain paths connected between ground and a positive power supply terminal (not shown) of the integrated circuit. The gates of the complementary transistors of inverters 46 and 48 are connected to the A.sub.0 and B.sub.0 outputs of sources 24 and 26, respectively. The drains of the complementary transistors in each inverter have a common terminal, such that the drains of the transistors of inverter 46 are tied to the gate of FET 43 and the common terminal of the drains of the transistors of inverter 48 is tied to the gate of FET 42.
In response to A.sub.0 =1 and B.sub.0 =0, the voltages at the gates of FETs 41 and 42 turn on the source drain paths of these FETs to provide a low impedance circuit between output terminal 28 and ground terminal 30. In response to A.sub.0 =0 and B.sub.0 =1, the voltages applied to the gates of FETs 43 and 44 turn on the source drain paths of these two FETs to couple the ground voltage at terminal 30 to output terminal 28. Values of A.sub.0 =1 and B.sub.0 =1 cause the source drain paths of FETs 41 and 44 to be turned off so that terminal 28 is decoupled from ground terminal 30. Similarly, but in an opposite manner, values of A.sub.0 =B.sub.0 =1 cause the source drain paths of transistors 43 and 42 to be turned off, so the ground voltage at terminal 28 is decoupled from terminal 30.
Output terminal 28 of comparator 10 is connected to lead 50, which is tied to the output terminals of all the remaining comparators 11, 12 . . . 16, 17. Lead 50 is coupled to the integrated circuit positive power supply voltage, +V.sub.dd, through the source drain path of P-channel FET 52, having a grounded gate. Lead 50 is coupled to an input of inverter 54 which is constructed the same as described supra for inverters 46 and 48 to derive a bi-level output that swings approximately between the DC power supply voltage +V.sub.dd and ground in response to the bi-level values on lead 50.
In response to the ground voltage at terminal 28 being coupled to ground terminal 30 through one of the two parallel paths of comparator 10, i.e., through either the series connection of FETs 41 and 42 or through the series connection of FETs 43 and 44, a low, virtually ground voltage is applied to lead 50. The low voltage on lead 50, in combination with the ground voltage on the gate of FET 52, causes the source drain path of FET 52 to be cut off to isolate lead 50 from the +V.sub.dd power supply voltage applied to the source of FET 52.
In response to FETs 41-44 of comparator 10 causing terminal 28 to be decoupled from ground terminal 30, while all of the remaining comparators 11, 12 . . . 16, 17 have the output terminals thereof decoupled from the ground terminals thereof, lead 50 is decoupled from the ground terminals. Decoupling lead 50 from the ground terminals of comparators 10, 11, 12 . . . 16, 17 causes the source drain path of FET 52 to be turned on by the ground voltage applied to the gate of FET 52. Thereby, the positive power supply voltage +V.sub.dd applied to the source of FET 52 is applied through the source drain path of FET 52 to lead 50 so the bus is at the high voltage associated with +V.sub.dd.
The circuit of FIG. 1 has several disadvantages. The transistor count for each of comparators 10, 11, 12 . . . 16, 17 is relatively high since six transistors are required in each comparator. Hence, to compare two 8-bit bytes, the eight comparators of FIG. 1 require 48 transistors. The six transistors in each comparator add significantly to the power requirements of the multi-bit comparator. The large number of transistors, in addition to requiring a significant amount of power, requires a significant amount of space on the integrated circuit chip and increases cost. The relatively large number of transistors required in the circuit of FIG. 1 also adversely affects performance because more transistors are required to pull down output terminals 28 of the comparators to ground.
It is, accordingly, an object of the present invention to provide a new and improved multi-bit comparator circuit.
Another object of the present invention is to provide a new and improved multi-bit comparator circuit for comparing like ordered bits of two bytes or words, wherein the circuit includes several comparators and is arranged so a binary signal having a value indicative of whether or not the binary bits have like values is derived.
Another object of the invention is to provide a new and improved multi-bit comparator circuit having a relatively low number of transistors, resulting in low cost, low power consumption, and reduced integrated circuit space requirements.
Another object of the invention is to provide a new and improved multi-bit comparator having relatively low capacitive loading of binary bit sources.